#include "um_tim.h"

//#include "stm32f10x.h"
#include "state.h"
//#include "freertos.h"
//#include "app_task_p.h"


UM_SYS_TimerFlag     UM_SYS_TIMER;

//must 1ms run one time
void UM_Systick_Handler()
{
	static u16 half_sec_cnt = 0;
	static u16 sec_cnt = 0;
	static u8  _100ms_cnt = 0;
	static u8  _10ms_cnt = 0;
	static u8  _5ms_cnt = 0;

    if ( ++_5ms_cnt == 5 )
    {
    	_5ms_cnt = 0;
    	UM_SYS_TIMER.sys_5ms_event = 1;
    }
    if ( ++_10ms_cnt == 10 )
    {
    	_10ms_cnt = 0;
    	UM_SYS_TIMER.sys_10ms_event = 1;
    }
    if ( ++_100ms_cnt == 10 )
	{
    	_100ms_cnt = 0;
		UM_SYS_TIMER.sys_100ms_event = 1;
	}

    if ( ++half_sec_cnt == 500 )
    {
    	half_sec_cnt = 0;
    	PostMessage(WM_TMR_HALF_SEC,0);
//    	_msg.message = WM_TMR_HALF_SEC;
//        xQueueSend( MsgQueue, ( void* )&_msg, 0 );
    }
    if ( ++sec_cnt == 1000 )
    {
    	sec_cnt = 0;
    	PostMessage(WM_TMR_SEC,0);
//    	_msg.message = WM_TMR_SEC;
//        xQueueSend( MsgQueue, ( void* )&_msg, 0 );
    	UM_SYS_TIMER.sys_sec++;
    }
    UM_SYS_TIMER.systicks++;
}


//// 36000   20  t=10ms    //3600,20 t=1ms
void UM_TimInit(TIM_TypeDef* TIMx,u16 Prescaler,u16 Period,u8 div)
{
    TIM_TimeBaseInitTypeDef    TIM_TimeBaseStruct;
    NVIC_InitTypeDef           NVIC_InitStructure;

	uint16_t clk_div = TIM_CKD_DIV1;
    if ( div == 2 )
    {
    	clk_div = TIM_CKD_DIV2;
    }
    else if ( div == 4 )
	{
    	clk_div = TIM_CKD_DIV4;
	}

    if ( TIMx == TIM1 )
    {
    	RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
    }
    else if ( TIMx == TIM2 )
    {
    	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
    }
    else if ( TIMx == TIM3 )
    {
    	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
    }
    else if ( TIMx == TIM4 )
    {
    	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
    }


    TIM_ClearITPendingBit(TIMx, TIM_IT_Update);
    TIM_TimeBaseStruct.TIM_Period = Period-1;
    TIM_TimeBaseStruct.TIM_Prescaler = Prescaler-1;
    TIM_TimeBaseStruct.TIM_ClockDivision = clk_div;
    TIM_TimeBaseStruct.TIM_CounterMode = TIM_CounterMode_Up;
    TIM_TimeBaseInit(TIMx, &TIM_TimeBaseStruct);

    TIM_ITConfig(TIMx, TIM_IT_Update, ENABLE);
    TIM_Cmd(TIMx, ENABLE);

    if ( TIMx == TIM1 )
    {
        NVIC_InitStructure.NVIC_IRQChannel = TIM1_IRQn;//TIM1_UP_IRQn;//TIM1_IRQn;

//        TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
//        TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
//        TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
//        TIM1_CC_IRQn
    }
    else if ( TIMx == TIM2 )
    {
        NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
    }
    else if ( TIMx == TIM3 )
    {
        NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
    }
    else if ( TIMx == TIM4 )
    {
        NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn;
    }
//    NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_Init(&NVIC_InitStructure);
}
